In a NOR flash memory being a kind of nonvolatile semiconductor, for example, a Multi Level Cell (MLC) scheme may be used which stores 2 bits in one cell. In a memory using the MLC scheme, as illustrated in FIG. 5, a threshold voltage Vt of a memory cell storing data corresponds to each data state. FIG. 5 illustrates a distribution of the threshold voltage of the NOR flash memory using the MLC scheme. In FIG. 5, the abscissa axis represents the threshold voltage Vt, and the ordinate axis represents the number of memory cells. Memory cells corresponding to data of 11 have a threshold voltage equal to or less than a voltage R1. Memory cells corresponding to data of 10 have a threshold voltage greater than the voltage R1 and less than a voltage R2. Memory cells corresponding to data of 01 have a threshold voltage greater than the voltage R2 and less than a voltage R3. Memory cells corresponding to data of 00 have a threshold voltage equal to or greater than a voltage R3.
When a reading operation is performed for memory cells using the MLC scheme, by controlling a voltage applied to the word line (WL) of a memory cell array in multi steps, the data of an accessed memory cell is determined. FIG. 6 is a diagram illustrating the change of a voltage Vg (i.e., a voltage Vg which is applied to a gate of a memory cell) applied through a word line with time.
A voltage Vg1 is one that is applied to a word line (WL) for determining a memory cell having a threshold voltage which corresponds to 11 and a memory cell having a threshold voltage which corresponds to 10 or a threshold voltage equal to or greater than it. A voltage Vg2 is one that is applied to a word line (WL) for determining a memory cell having a threshold voltage which corresponds to 10 or a threshold voltage equal to or less than it and a memory cell having a threshold voltage which corresponds to 01 or a threshold voltage equal to or greater than it. A voltage Vg3 is one that is applied to a word line (WL) for determining a memory cell having a threshold voltage which corresponds to 01 or a threshold voltage equal to or less than it and a memory cell having a threshold voltage which corresponds to 00.
For implementing the NOR flash memory using the MLC scheme, a word line decoder for driving a memory cell needs operate at a high speed. Such an operation time is one of important factors for determining a read speed.
A word line decoder of FIG. 7 is used in a speeding-up method. A word line decoder 120 of a memory cell array 110 separates a well voltage Vwell and a source voltage Vwl, thereby minimizing a capacity that is driven with the source voltage Vwl. As a result, a driving speed is sped up when a word line level is shifted as illustrated in FIG. 6. In this configuration, a potential relationship of “Vwell≧Vwl” is always required for suppressing the current of a pn direction in the word line decoder 120. FIG. 8 illustrates relationships between a word line driving voltage Vg, a well voltage Vwell and a source voltage Vwl in a reading operation. In FIG. 8, the well voltage Vwell is controlled with a certain value, and the source voltage Vwl is controlled to incrementally be changed. In this way, by controlling the well voltage Vwell with a certain value and simultaneously changing only the source voltage Vwl having a small driving capacity, a time necessary for operation is shortened.
Moreover, a semiconductor device 100 in FIG. 7 includes a plurality of blocks 101-0 to 101-i, a global bit line selection block 102, and a sense amplifier block 103. Each of the blocks 101-0 to 101-i include a memory cell array 110, and the memory cell array 110 includes nonvolatile memory cells 111 using an MLC scheme. Each of the blocks 101-1 to 101-i include a word line decoder 120 and a local bit line selection block 130.
The memory cell array 110 includes a plurality of nonvolatile memory cells 111 using the MLC scheme. The gate of the each nonvolatile memory cell 111 is connected to a word line WL, and the drain of the each nonvolatile memory cell 111 is connected to a local bit line LBL.
The word line decoder 120 includes a plurality of word line drivers that have a PMOS transistor 121 and an NMOS transistor 122. In this case, the source voltage Vwl and the well voltage Vwell are applied to the source and well of the PMOS transistor 121, respectively.
The local bit line selection block 130 includes a plurality of NMOS transistors 131 that connect a local bit line selected from among local bit lines LBL to a global bit line GBL. In this case, signals YL0 and YL1 are applied to the gates of the NMOS transistors 131, respectively.
The global bit line selection block 102 includes a plurality of NMOS transistors 141 for selecting global bit lines GBL. In this case, signals YG0 and YG1 are applied to the gates of the NMOS transistors 141, respectively.
The sense amplifier block 103 includes a plurality of sense amplifiers 151. The sense amplifiers 151 amplify data that is transferred through a selected global bit line, and a global bit line is selected by the global bit line selection block 102.
When a writing operation is performed, the level of a word line need be set as a higher potential than the potential of a word line in a reading operation. Accordingly, for example, when being changed from a reading state to a writing state, a source voltage Vwl and a well voltage Vwell need be shifted to have a higher potential together. In this case, the capacity of the well voltage Vwell is much greater than that of the source voltage Vwl. Accordingly, for example, as illustrated in FIG. 9, a state of “Vwell<Vwl” is easily generated in a regulator that has the same control and driving ability. That is, the reverse of a pn potential is easily generated. When the reverse of the pn potential exceeds a diode order direction potential Vf, a severe failure of a device is caused. Accordingly, scrupulous care is required in designing.
FIG. 9 illustrates an example where a word line driving voltage Vg, a well voltage Vwell and a source voltage Vwl are shifted with time in a writing operation. The following first and second methods are examples of a method that shifts the potential level of a source voltage Vwl and the potential level of a well voltage Vwell while maintaining a relationship of “Vwell≧Vwl”.
As illustrated in FIG. 10, a well voltage Vwell is first charged. The charging of the well voltage Vwell is completed, and then the charging operation of a source voltage Vwll is started. In such a method, times are required for completing the charging of the well voltage Vwell and well voltage Vwell.
As illustrated in FIG. 11, a source voltage Vwl is outputted to always maintain a relationship of “Vwell≧Vwl” based on the driving capacity of a source voltage Vwl, the driving capacity of a well voltage Vwell and wiring delay. The driving ability of a regulator for satisfying this or the driving ability of a regulator for outputting the well voltage Vwell is designed. In this case, there is a requirement for satisfying all factors such as the operating condition of the source voltage Vwl, the operating condition of the well voltage Vwell, an external temperature and the manufacturing deviation of an element in a chip. Accordingly, it is difficult to design a circuit.
FIGS. 10 and 11 illustrate an example where a word line driving voltage Vg, a well voltage Vwell and a source voltage Vwl are shifted with time in the first and second methods.
An example of configuration of a power source circuit for implementing the first or second method will be described below with reference to FIG. 12. FIG. 12 is a circuit diagram illustrating the configuration of a voltage stabilization device 50. The voltage stabilization device 50 may be referred to as a regulator 50. The regulator 50 includes an operational amplifier 51, a PMOS transistor 52, a resistor 53, a resistor 54, a PMOS transistor 55, and a level shifter circuit (LS) 56.
A reference voltage Vref5 is applied to the non-inversion input terminal of the operational amplifier 51. A connection node between the serially-connected resistors 53 and 54 is connected to the inversion input terminal of the operational amplifier 51. The output terminal of the operational amplifier 51 is connected to the gate of the PMOS transistor 52. The source of the PMOS transistor 52 is connected to a power source supplying a voltage Vh, and the drain of the PMOS transistor 52 is connected to the resistor 53. The PMOS transistor 52 is an active load for an output voltage Vwl. That is, the drain of the PMOS transistor 52 is connected to the output voltage Vwl. The resistor 54 is connected to a ground terminal.
The level shift circuit 56 shifts the level of a trim signal by using a voltage (i.e., Vwl) applied from the resistor 53 as a power source voltage. The level shift circuit 56 turns on/off the PMOS transistor 55 according to the level of the trim signal. When the trim signal has a high level (H), the PMOS transistor 55 is turned on. When the trim signal has a low level (L), the PMOS transistor 55 is turned off. The drain and source of the PMOS transistor 55 are connected to certain two points of the resistor 53. A resistance-divided voltage ratio (or resistance division ratio) by the resistors 53 and 54 is changed according to the turn-on/off of the PMOS transistor 55.
In the regulator 50, the operational amplifier 51 compares a difference between the reference voltage Vref5 and the resistance-divided voltage of the output voltage Vwl, and controls a voltage that is applied to the gate of the PMOS transistor 52 according to the compared result. Accordingly, a constant output voltage Vwl is maintained.
The output voltage Vwl is shifted. In this case, a resistance-divided voltage ratio is changed by a trim signal. The second method adjusts the gate width of the PMOS transistor 52 to adjust a charging performance. The first method adjusts timing when the output voltage Vwl is activated or timing (which is the changed timing of the trim signal) when a resistance-divided voltage ratio is changed. In a case of designing in the first or second method in order for the reverse of a pn potential not to occur, it is difficult to control a power source in a short time.
A related art has been disclosed in patent documents 1 to 4. In the patent document 1, when an internal voltage VI1 applied to a well and an internal voltage applied to a source are generated, the internal voltage VI1 is generated by a first step-down circuit and the internal voltage VI2 is generated by a second step-down circuit (see FIG. 1 and FIG. 6B of the patent document 1). Technology that shortens the charging time of a load capacity by the internal voltage VI2 has been disclosed in the FIG. 2 and paragraph 0028 to 0031 of the patent document 1.
In a case of designing in the first or second method in order for the reverse of a pn potential not to occur, it is difficult to control a power source in a short time. Also, as described in the patent document 1, in a case that uses the output (first voltage) of a first step-down circuit as the power source of a second step-down circuit among two step-down circuits, the charging performance of a second voltage is degraded when the output (second voltage) of the second step-down circuit approaches the first voltage.